TW3811 SLOC Receiver Datasheet

TW3811 Security Link Over Coax (SLOC) Receiver DATASHEET

Published Time: Thu, 16 Jan 2025 04:10:04 GMT

Number of Pages: 20

FN8284 Rev.1.00 Page 1 of 20 Nov 29, 2012

SLOC™ (Security Link Over Coax) is a transmission protocol for simultaneously transmitting analog CVBS video and digital IP video over a single coaxial cable. The TW3811 is the receiving end of a SLOC link, converting the single SLOC signal on the coaxial cable back to separate Ethernet digital video data and analog CVBS video. It can be embedded into a DVR to enable one or more SLOC inputs or configured as a stand-alone SLOC-to-IP+CVBS converter. The TW3811 includes an AFE, digital modem, and two Ethernet MII/RMII interfaces. The device accepts a SLOC output signal from a SLOC transmitter and decodes it into an analog CVBS signal and an Ethernet MII signal.

Applications

Single-Channel SLOC receiver modem
Multi-Channel SLOC receiver modem
Embedded DVR

Features

Simultaneous transmission of IP video data and analog CVBS video over up to 500m of RG59 coaxial cable
Analog CVBS video preview support
Proprietary adaptive analog equalizer for extending the reach of CVBS video
Proprietary SLOC-based IP camera detection
Creates a full-duplex 100BASE-T digital link
36Mbps downlink speed from TW3801 to TW3811
4Mbps uplink for SLOC compliance
Ethernet MAC MII/RMII interface for interfacing to DVR/NVR network processor SoC
Optional Ethernet PHY MII/RMII interface for interfacing to external Ethernet PHY chip
I 2C 2-wire control interface
Integrated PLL with 25MHz crystal interface
1.8V, 3.3V supplies
100-TQFP (12x12mm) Package

Application Block Diagram

EL8101
Analog CVBS Ethernet SPOT Monitor DVR Network Switch NVR
One-Channel SLOC Receiver
TW3811 100BASE-T PHY
SLOC Adapter Module
TW3801
Up to 500m of RG59 cable
IP Camera Analog CVBS Ethernet 100BASE-T PHY MCU
(optional)
MCU
(optional)

Simplified Application Schematic

3.3V 3.3V 1.8V +
TW3811
+COAX_OUT 22μF 0.1μF 470μF 75 COAX_IN 1M 25MHz 22pF 22pF XTAL_OUT XTAL_IN 10k 10μF 24k CVBS_OUT 1.5k 10μF 4.7k 3.3V I2CMicrocontroller SCL SDA MII or RMII PHY MII / RMII Interface RJ45 Ethernet I/O SLOC Coax I/O LOAD_DRV 75 VDD_IO VDD_A VDD_D 150nH BAT54 75 + CVBS Output 470μF

TW3811 FN8284 Rev.1.00 Page 2 of 20 Nov 29, 2012

Pin Configuration TW3811 (100 LD TQFP) TOP VIEW

99 VDD_IO 100 VSS_IO
2356RX_D1 A8 VDD_D 9 VSS_D 11 RX_D2 A12 RX_D3 A14 TX_EN A15 17 18 20 21 23 24 78 COAX_IN 77 NC 76 VSS_A 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 49 48 31 29 34 32 37 36 VDD_IO 39 40 41 42 44 43 45 47 46 50 98 HWRST 97 SCLK 96 VSS_D 95 VDD_D 94 SDA 93 92 91 MODE_S1 90 VSS_D 89 VDD_D 88 MODE_S0 87 VSS_IO 86 VDD_IO 85 XTAL_OUT 84 XTAL_IN 83 VSS_PLL 82 VDD_PLL 81 VDD_DAC 80 VREF 79 VSS_DAC 38 14710 13 16 19 22 25 27 28 30 26 33 35 TW3811 100-pin TQFP (12x12) VDD_IO VSS_IO MDC MDIO RX_DV ARX_ER ARX_D0 ANC VDD_D VSS_D VDD_IO VSS_IO TX_D0 ATX_D1 ATX_D2 ARX_CLK ATX_D3 ATX_ER ATX_CLK ATX_ER BVSS_IO TX_EN BTX_D0 BTX_D1 BTX_D2 BTX_D3 BTX_CLK BVDD_D VSS_D VDD_D VSS_D RX_CLK BRX_ER BRX_DV BRX_D0 BRX_D1 BVDD_IO VSS_IO RX_D2 BRX_D3 BTEST_IN0 TEST_IN1 TEST_IO VDD_IO VSS_IO VDD_D VSS_D LED_0 LED_1 LED_2 A0 A1 VSS_ADC COM_ADC REFN_ADC REFP_ADC VDD_ADC VDD_DRV LOAD_DRV COAX_OUT NC NC CVBS_OUT VDD_TVDR VSS_DRV VSS_TVDR VDD_A COM_REF MODE_S2 MODE_S3

TW3811 FN8284 Rev.1.00 Page 3 of 20 Nov 29, 2012

Pin Descriptions

SYMBOL	NUMBER	DESCRIPTION
POWER SUPPLY AND GROUND
VDD_IO	1, 23, 27, 48, 51, 86, 99	3.3V Power supply for all digital I/Os. Connect to the 3.3V supply through a MI0805K601R-10 (or equivalent) ferrite bead and bypass each supply pin to ground plane with a 0.1 μF capacitor.
VSS_IO	2, 24, 28, 49, 52, 87, 100	Digital I/O Ground. Connect each pin to ground plane using the shortest/lowest inductance path possible.
VDD_D	8, 15, 34, 42 58, 89, 95	1.8V Power supply for core digital logic. Connect to the 1.8V supply through a MI0805K601R-10 (or equivalent) ferrite bead and bypass each supply pin to ground plane with a 0.1 μF capacitor.
VSS_D	9, 16, 35, 43 59, 90, 96	Digital Core Ground. Connect each pin to ground plane using the shortest/lowest inductance path possible.
VDD_ADC	64	3.3V Power supply for internal ADC. Connect to the 3.3V supply through a MI0805K601R-10 (or equivalent) ferrite bead and bypass to ground plane with a 0.1 μF capacitor.
VSS_ADC	60	ADC Analog Ground. Connect to ground plane using the shortest/lowest inductance path possible.
VDD_DRV	65	3.3V Power supply for analog output stages. Connect to the 3.3V supply through a MI0805K601R-10 (or equivalent) ferrite bead and bypass to ground plane with a 0.1 μF capacitor.
VSS_DRV	70	Analog Output Driver Ground. Connect to ground plane using the shortest/lowest inductance path possible.
VDD_A	71, 74	3.3V Power supply for internal analog. Connect to the 3.3V supply through a MI0805K601R-10 (or equivalent) ferrite bead and bypass each pin to ground plane with a 0.1 μF capacitor.
VSS_A	73, 76	Analog Ground. Connect each pin to ground plane using the shortest/lowest inductance path possible.
VDD_DAC	81	3.3V Power supply for DAC. Connect to the 3.3V supply through a MI0805K601R-10 (or equivalent) ferrite bead and bypass to ground plane with a 0.1 μF capacitor.
VSS_DAC	79	DAC Analog Ground. Connect to ground plane using the shortest/lowest inductance path possible.
VDD_PLL	82	3.3V Power supply for PLL. Connect to the 3.3V supply through a MI0805K601R-10 (or equivalent) ferrite bead and bypass to ground plane with a 0.1 μF capacitor.
VSS_PLL	83	PLL Analog Ground. Connect to ground plane using the shortest/lowest inductance path possible.
ANALOG
ADC_COM	61	Analog Output. Internally Generated ADC Reference Voltage. Common mode reference voltage for ADC. Bypass to ground plane with a 0.1 μF capacitor.
ADC_REFN	62	Analog Output. Internally Generated ADC Reference Voltage. Negative differential reference voltage for ADC. Bypass to ground plane with a 0.1 μF capacitor.
ADC_ REFP	63	Analog Output. Internally Generated ADC Reference Voltage. Positive differential reference voltage for ADC. Bypass to ground plane with a 0.1 μF capacitor.
LOAD_DRV	66	Analog Output. Driver Reference Load. The signal on this pin generates the output current that is mirrored onto the COAX_OUT pin. Connect to a 75 Ω, 1% resistor to ground. To maximize stability, ensure that this signal is isolated from the COAX_OUT signal. This can be achieved by placing the resistor on the bottom side of PCB and routing the trace in the opposite direction from the COAX_OUT trace.
COAX_OUT	67	Analog Output. Coaxial TX Output. This pin is a high impedance current source output. Terminate to VSS_A with a 75 Ω 1% resistor in series with a 150nH inductor. AC-couple per Figure 1 to SLOC I/O connector.
CVBS_OUT	68	Analog Output. Inverted CVBS output. Connect an EL8101 in the inverting mode for a gain of -2. Refer to reference schematic for more details.
COM_REF	75	Analog Output. Internally Generated Reference Voltage. Bypass to ground plane with a 0.1 μF capacitor.
COAX_IN	78	Analog Input. Coaxial RX Input.
VREF	80	Analog Input. Externally Generated Reference Voltage. Voltage reference input for internal DAC. Connect to a 1.2VDC source. This voltage can be generated from AVD_DAC with a 6.34k/3.65k Ω resistor divider and 0.1 μF bypass capacitor. Refer to reference schematic for more details.

TW3811 FN8284 Rev.1.00 Page 4 of 20 Nov 29, 2012

SYMBOL	NUMBER	DESCRIPTION
XTAL_IN	84	Analog Input. Crystal Input. Connect to one end of a 25MHz crystal with 22pF capacitor and 1M Ω feedback resistor. Refer to reference schematic for more details.
XTAL_OUT	85	Analog Output. Crystal Output. Connect to other end of a 25MHz crystal with 22pF capacitor and 1M Ω feedback resistor. Refer to reference schematic for more details.
MII/RMII DIGITAL INTERFACE
MDC	3	Digital Output. MDC is the management data clock reference for the serial management interface. The maximum frequency supported is 3.125MHz
MDIO	4	Digital I/O. MDIO is the management data. MDIO transfers data synchronously with MDC.
The following pins are used to connect TW3811 to an external Ethernet PHY using the A Interface pins, when MODE_S3 = 0.
RX_DV A	5	Digital Input with internal 57k Ω pull-down resistor to VSS_IO. Receive Data Valid. 0: The incoming data on the RX_Dn A is not ready to be latched. 1: The incoming data on the RX_Dn A pins is valid and should be latched using RX_CLK A .
RX_ER A	6	Digital Input with internal 57k Ω pull-down resistor to VSS_IO. Receive Error 0: The incoming data on the RX_Dn A pins is valid. 1: The incoming data on the RX_Dn A pins has an error.
RX_D0 A	7	Digital Input with internal 57k Ω pull-down resistor to VSS_IO. Receive Data bit 0.
RX_D1 A	10	Digital Input with internal 57k Ω pull-down resistor to VSS_IO. Receive Data bit 1.
RX_D2 A	11	Digital Input with internal 57k Ω pull-down resistor to VSS_IO. Receive Data bit 2. (MII mode only)
RX_D3 A	12	Digital Input with internal 57k Ω pull-down resistor to VSS_IO. Receive Data bit 3. (MII mode only)
TX_EN A	14	Digital Output. Transmit Enable. 0: Data on the TX_Dn A pins is not ready. 1: Data on the TX_Dn A pins is valid and should be latched using TX_CLK A .
TX_ER A	17	Digital Output. Transmit Error. This pin is normally low. When in “Passthrough Mode”, this pin duplicates the state of TX_ER B .
TX_D0 A	18	Digital Output. Transmit Data bit 0.
TX_D1 A	19	Digital Output. Transmit Data bit 1.
TX_D2 A	20	Digital Output. Transmit Data bit 2. (MII mode only)
TX_D3 A	21	Digital Output. Transmit Data bit 3. (MII mode only)
RX_CLK A	22	Digital Input with internal 57k Ω pull-down resistor to VSS_IO. Receive Data Clock signal.
TX_CLK A